How does the hardware x86_64 4-level page table walk translate a 48-bit virtual address into a physical address?

On 64-bit x86_64 systems using 4-level paging (canonical 48-bit virtual address space), address translation is executed entirely in CPU hardware: (1) The CPU reads the physical base address of the Page Global Directory (PGD) from the CR3 register; (2) Bits 47:39 (9 bits, 512 entries) index into the PGD to locate a Page Upper Directory (PUD) pointer; (3) Bits 38:30 (9 bits) index into the PUD to locate a Page Middle Directory (PMD) pointer; (4) Bits 29:21 (9 bits) index into the PMD to locate a Page Table Entry (PTE) pointer; (5) Bits 20:12 (9 bits) index into the PTE to find the physical frame address; (6) Bits 11:0 (12 bits) represent the byte offset within the 4KB page. If any intermediate entry has its Present bit set to 0, the MMU triggers a Page Fault (#PF) interrupt, pausing the thread while the kernel allocates memory or swaps in the page from disk.

What is a Translation Lookaside Buffer (TLB) miss, and what is the latency cost of a multi-level page walk?

The Translation Lookaside Buffer (TLB) is an associative hardware CPU cache that stores recently resolved virtual-to-physical address translations. When a memory access hits the L1 data TLB, address translation takes approximately 1 to 2 CPU clock cycles (~0.5 ns). When a TLB miss occurs, the CPU Memory Management Unit (MMU) must execute a Page Walk: traversing all 4 levels of page tables in physical RAM. In the worst case where intermediate page tables are not cached in the L3 CPU cache, each dereference requires a full DRAM access (~60 to 80 ns). A 4-level page walk can consume 250 to 320 ns (over 800 CPU clock cycles!) of complete pipeline stall for a single memory instruction. In memory-intensive workloads like in-memory databases, TLB misses can consume over 30% to 50% of total CPU cycles.

What is an Inter-Processor Interrupt (IPI) TLB shootdown and why does it cause severe multicore latency spikes?

When the Linux kernel modifies or unmaps a page table entry that is shared across multiple CPU cores (e.g. during memory compaction, page migration across NUMA nodes, or munmap()), the stale translation cached in other CPU TLBs must be immediately invalidated. Because one CPU cannot directly invalidate another CPU TLB, the initiating core must send an Inter-Processor Interrupt (IPI) to all target cores. The target cores must pause whatever user code they are executing, enter kernel interrupt context, execute the invlpg or mov cr3 instruction, and send an acknowledgment. On 64-core or 128-core NUMA systems, high-frequency TLB shootdowns cause catastrophic performance degradation, serializing parallel threads on hardware interrupt spinlocks.

How do Transparent HugePages (THP) differ from static HugeTLB (hugetlbfs)?

Linux provides two HugePage implementations: (1) Static HugeTLB (hugetlbfs): System administrators pre-allocate a fixed pool of 2MB or 1GB pages at boot time (e.g. hugepagesz=1G hugepages=64). Applications explicitly map these pages via mmap(MAP_HUGETLB) or shmget(). HugeTLB pages are pinned in RAM, never swapped, and never fragmented, providing 100% deterministic low TLB miss rates. (2) Transparent HugePages (THP): An automatic kernel subsystem that dynamically allocates 2MB contiguous pages for anonymous memory without requiring application modifications. A background kernel daemon (khugepaged) continuously scans memory, compacts 4KB pages, and collapses them into 2MB HugePages. While convenient, THP introduces non-deterministic latency spikes during memory compaction.

Why do databases like Redis, PostgreSQL, and MongoDB explicitly advise disabling Transparent HugePages (THP)?

Database engines recommend disabling THP because of two severe architectural side-effects: (1) Latency Spikes during Copy-on-Write: Redis relies heavily on fork() for background RDB snapshot persistence. When THP is enabled, modifying a single 4-byte counter forces the kernel to copy an entire 2MB HugePage rather than a lightweight 4KB page (a 512x write amplification penalty!). This causes multi-millisecond request latency freezes. (2) Memory Compaction Jitter: When memory becomes fragmented, the kernel synchronous memory compaction path stalls user-space memory allocations while attempting to defragment 2MB contiguous physical blocks, causing sporadic p99 and p99.9 latency spikes.

How much physical RAM is consumed by page tables alone for a 1 TB virtual memory allocation with 4KB vs 2MB pages?

A 1 TB virtual address space contains 1,099,511,627,776 bytes. With standard 4KB pages, 1 TB requires 268,435,456 page table entries (PTEs). Each PTE consumes 8 bytes in memory, requiring 2,147,483,648 bytes (2 GB) of unswappable kernel RAM just for the PTE leaf tables, plus another ~4 MB for intermediate PMD and PUD tables. For an enterprise database running 500 parallel backend connection processes (each with their own page tables), page tables alone would consume over 1,000 GB of RAM! With 2MB HugePages, 1 TB requires only 524,288 entries at the PMD level (bypassing PTE leaf tables entirely), slashing page table memory consumption from 2,000 MB down to just 4.1 MB (a 99.8% memory savings!).

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x86_64 4-Level Paging 2MB / 1GB HugePages TLB Shootdown Profiler

Linux Page Tables, TLB Shootdowns & HugePages Architecture Studio

Master hardware virtual memory architectures: trace x86_64 4-level address translation walks (CR3 → PGD → PUD → PMD → PTE), calculate TLB miss stall penalties and multi-core IPI TLB shootdown latency spikes, and evaluate memory savings between 4KB, 2MB, and 1GB page tables.

4 KB Standard

Page Frame Size

2,048 MB (2.0 GB)

Page Table RAM Overhead

6.0 MB (1,536 entries)

L2 TLB Memory Reach

280 ns (840 cycles)

Worst-Case Page Walk Latency

madvise (Tuned)

THP Kernel Recommendation

~8.5 μs / shootdown

IPI TLB Shootdown Latency

1. 48-Bit Virtual Address Translation & Page Table Walk

Input a 64-bit virtual memory address to observe its exact bitfield indexing across PGD, PUD, PMD, and PTE

PGD Index [47:39]
0x0ff (255)

PUD Index [38:30]
0x1fd (509)

PMD Index [29:21]
0x1eb (491)

PTE Index [20:12]
0x1ff (511)

Offset [11:0]
0x840 (2,112 B)

CR3 Register
Physical Root: 0x104000

→

PGD Entry
Index 255 → PUD

→

PUD Entry
Index 509 → PMD

→

PMD Entry
Index 491 → PTE

→

PTE Entry
Index 511 → PFN

→

Physical RAM Frame
PFN 0x38b20 + Offset 0x840

2. Page Table Memory Footprint & TLB Reach Calculator

Virtual Address Space Size

Page Size Architecture

CPU L2 TLB Entries

Total Page Table Entries (PTEs): 268,435,456 Entries

Page Table Kernel RAM Consumption: 2,048.0 MB (2.0 GB per process!)

L2 TLB Memory Reach: 6.0 MB (Only 0.0006% of RAM cached in TLB!)

TLB Reach with 2MB HugePages: 3,072.0 MB (3.0 GB — 512x increase!)

Linux Page Tables, TLB Shootdowns & HugePages Architecture Studio

1. 48-Bit Virtual Address Translation & Page Table Walk

2. Page Table Memory Footprint & TLB Reach Calculator

3. Production HugePages & Memory Tuning Blueprints

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